Espressif Systems /ESP32 /TIMG0 /WDTCONFIG5

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Interpret as WDTCONFIG5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WDT_STG3_HOLD

Fields

WDT_STG3_HOLD

Stage 3 timeout value in SWDT clock cycles

Links

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